-- 32 bits 1 of 4 multiplexor
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---------------------------------------------------------------------------------

entity MUX_1_OF_4 is
	port(
		A 		:	in 	std_logic_vector(31 downto 0);
		B 		:	in 	std_logic_vector(31 downto 0);
		C 		: 	in 	std_logic_vector(31 downto 0);
		D 		:	in 	std_logic_vector(31 downto 0);
		SEL 	:	in 	std_logic_vector(1 downto 0);
		Y		:	out 	std_logic_vector(31 downto 0)
	);
end MUX_1_OF_4;

architecture Behavioral of MUX_1_OF_4 is

begin

	Y  <=  A when SEL="00" else
			 B when SEL="01" else
			 C when SEL="10" else
			 D;

end Behavioral;

